1. Field of the Invention
The present invention relates to an input/output channel apparatus for executing the input/output operations between a main memory device and an input/output apparatus in an electronic computer.
2. Description of the Prior Art
FIG. 7 is a diagram showing an example of a conventional input/output channel apparatus. In the diagram, reference numeral 1 denotes a central processing unit (CPU) to control the arithmetic operation processing operation of the whole apparatus; 2 indicates a main memory device to store data of the CPU 1; 3 an input/output channel apparatus to control the input/output to/from the CPU 1; 4 external input/output apparatuses which are connected to the CPU 1; 5 a channel processing section to process an input and an output of each channel of the input/output channel apparatus 3; 6 a main memory interface section to adjust signals front the main memory device 2 to the input/output channel apparatus 3; 7 channels CH.sub.0 to CH.sub.7 which are provided in correspondence with the input/output apparatuses 4; channel control sections 71 of the channels CH.sub.0 to CH.sub.7 (7); 72 data buffers of the channels CH.sub.0 to CH.sub.7 (7); 21 a CCW list of channel command words (hereinafter, referred to as CCW) which are prepared in the main memory device 2; 11 data buses connecting the main memory interface section 6 and the data buffers 72 of the channels CH.sub.0 to CH.sub.7 (7); 12 control buses connecting the channel processing section 5 and the channel control sections 71 of the channels CH.sub.0 to CH.sub.7 (7); and 13 input/output interfaces connecting the data buffers 72 of the channels CH.sub.0 to CH.sub.7 (7) and the input/output apparatuses 4.
The operation of the conventional input/output channel apparatus based on the above construction will now be described with reference to FIGS. 8 and 9. FIG. 8 is a graph showing the transfer speed to time characteristics with respect to the data transfer speed control in prefetching from the main memory device 2 to the data buffers in the conventional apparatus. FIG. 9 is a graph showing the transfer speed to time characteristics of the data transfer speed (a solid line indicates a total data transfer speed and a broken line represents a transfer speed in every channel) in the main memory interface section in time conventional apparatus.
In the diagrams, an input/output start command is first supplied from the CPU 1 to the channel processing section 5. The channel processing section 5 selects the channels CH.sub.i (i=0 to 7) 7 on the basis of a channel address designated by the I/O start command. The channel processing section 5 generates the input/output command designated by the I/O start command to the corresponding I/O apparatus 4 through the I/O interface 13 of the channel CH.sub.i 7 on the basis of the I/O address designated by the I/O start command.
A write command will now be considered as an I/O command. Next, the channel processing section 5 requests for prefetching of write data to the channel CH.sub.i 7. Then, the channel CH.sub.i 7 starts prefetching the data into the data buffer 72 from the main memory device 2 through the main memory interface section 6. The data prefetched in the data buffer 72 is transferred to the corresponding I/O apparatus 4 through the I/O interface 13 of the channel CH.sub.i 7.
When the data to be written is prefetched, as shown in FIG. 8, it is prefetched at the maximum transfer speed from the main memory device 2 until the data buffer 72 is filled with the data and, after the data buffer 72 has been filled with the data, the data is continuously prefetched at the same transfer speed as that between the data buffer 72 and the I/O apparatus 4.
When the I/O start commands are successively inputted to all of the channels CH.sub.0 to CH.sub.7 (7) and each channel CH.sub.i 7 has completely prefetched the data to be written as shown in FIG. 8, the data transfer speed in the main memory interface section 6 increases until the total value (the peak point of the transfer speed in the diagram) of the maximum transfer speeds of the prefetching of the channels CH.sub.i 7 as shown in FIG. 9.
The operation In the case where the above conventional I/O channel apparatus executes the data chaining process will now be described with reference to FIGS. 10 to 12.
FIG. 10 is a CCW list state diagram showing an example of the CCW list 21. In the diagram, reference numeral 14 denotes a CCW comprising two words; 15 indicates a command code indicative of the reading or writing operation; 16 a data address indicative of a start address of data transfer; 17 a byte count indicative of the number of bytes to be transferred; and 18 a data chain flag in a flag byte provided to indicate a data chain command. FIG. 11 is a flowchart showing all example of a processing flow of the data chain which Is executed by the channel control section 8.
FIG. 12 is a data buffer storage state diagram showing the steps in which the data which was read out of the I/O apparatus 4 is stored into the data buffer 72 before and after the data chain. In the diagram, reference numeral 19 denotes data which had already been read out of the I/O apparatus 4 by the channel control section 71 when the data transfer to the main memory device 2 which was indicated by a CCW.sub.m has been all completed. Reference numeral 20 indicates data which was read out of the I/O apparatus 4 for the period of time when the channel control section 71 executes the data chaining process from the CCW.sub.m to CCW.sub.m+1.
In the diagrams, the CPU 1 prepares the CCW list 21 in the main memory device 2 and generates the input/output start command (hereinafter, referred to as START I/O) to the channel processing section 5. Thus, the channel processing section 5 reads the head CCW.sub.1 from the CCW list 21 in the main memory device 2 via the main memory interface section 6. Next, the channel processing section 5 selects the channel CH.sub.i (i=0 to 7) 7 designated by the START I/O and sends the CCW.sub.1 to the channel control section 71 of the same channel CH.sub.i 7 via the control bus 12. Then, the channel control section 71 supplies the command code 15 (refer to FIG. 10) in the CCW.sub.1 to the I/O apparatus 4 designated by the START I/O. A read command, that is, a data transfer command from the I/O apparatus 4 to the main memory device 2 is now considered as the command code.
The activated I/O apparatus 4 transfers the read data to the channel CH.sub.i 7 through the I/O interface 13. The channel control section 71 of the same channel CH.sub.i 7 temporarily stores the read data into the corresponding data buffer 72. The channel control section 71 sequentially writes the read data stored in the data buffer 72 into the main memory device 2 via the data buses 11 and main memory interface section 6 in accordance with the order from the data address 16 (refer to FIG. 10) in the CCW.sub.1. In this manner, the read command designated by the CCW.sub.1 is executed.
As mentioned above, the data transfer is executed and when the data of the amount designated by the byte count 17 (refer to FIG. 10) in the CCW.sub.1 has been completely transferred into the main memory device 2, the channel control section 71 of the channel CH.sub.i 7 checks the data chain flag 18 (refer to FIG. 10) in the CCW.sub.1 in accordance with the processing flow of FIG. 11. If the flag 18 is set to 1, it is regarded that the data chain command has been generated. The channel control section 71 makes a request for the next CCW.sub.2 to the channel processing section 5 via the control bus 12.
In response to the request, the channel processing section 5 reads out the CCW.sub.2 from the CCW list 21 in the main memory device 2 via the main memory interface section 6 and returns the CCW.sub.2 through the control bus 12 to the channel control section 71 which made the request.
In response to the CCW.sub.2, the channel control section 71 executes the data chaining process from the CCW.sub.1 to the CCW.sub.2 to allow the data transfer to the main memory device 2 to be continued by using the data address 16 and byte count 17 (refer to FIG. 10) in the CCW.sub.2.
FIG. 12 shows a change in the amount of data in the data buffer 72 before and after the data chain. In the diagram, upon completion of the data transfer to the main memory device 2 designated by the CCW.sub.1, the data 19 to be transferred to the main memory device 2 has already been read out of the I/O apparatus 4 and stored into the data buffer 72 on the basis of the next CCW.sub.2.
On the other hand, upon completion of the data chaining process from the CCW.sub.1 to the CCW.sub.2, in addition to the data 19, the data 20 which was read out of the I/O apparatus 4 for the period of time when the data chaining process was being executed by using the CCW.sub.2 is stored. This is because during the above period of time, for the I/O apparatus 4, the data transfer to the channel CH.sub.i 7 is continued irrespective of the presence or absence of the data chain, while the data transfer to the main memory device 2 is temporarily interrupted. When the data chaining process from the CCW.sub.1 to the CCW.sub.2 by the channel control section 71 is finished, the data 19 and 20 (refer to FIG. 12) in the data buffer 72 are again transferred to the main memory device 2.
As mentioned above, when the execution of all of the CCW.sub.1 to CCW.sub.n in the CCW list 21 has been completed, all of the input and output operations which were started by the START I/O are completed.
Since the conventional input/output channel apparatus has been constructed and controlled as mentioned above, the maximum value of the data transfer speed between the I/O channel apparatus and the main memory device must be set to a high value. If the data transfer speed does not satisfy the maximum value, problems result whereby data transfer among the channels is interfered with and a data overrun can easily occur between the I/O apparatus and the main memory device. There is also problem that such a data overrun can occur not only during the execution of the write command but also during the execution of the read command if a channel which is simultaneously executing the read command exists.
Further, since the conventional input/output channel apparatus has been constructed and controlled as mentioned above, there are problems such that if data chains simultaneously occur in a plurality of channels which are executing the read command, in which the transfer of the CCW from the channel processing section 5 to the channel control section 71 is delayed in some channels, the amount of data 19 and 20 to be stored in the data buffer of such a channel exceeds the capacity of the data buffer, so that a data overrun occurs between the channel CH.sub.i 7 and the input/output apparatus 4.